1. Technical Field
The present invention relates to a wireless data communication demodulation method of receiving and demodulating a transmission packet, a former half of which is sent by a frequency shift keying modulating signal and a latter half of which is sent by a phase-shift keying modulating signal.
2. Background Art
In general, in a short distance wireless data communication system using an ISM band of 2.4 GHz, a transmission packet is sent by a frequency shift keying modulating signal, and frequency shift keying demodulation is performed on a reception side as well.
In such short distance wireless data communication, a transmission packet, which is constituted by a scramble code, a header, and a payload, is sent. However, due to a demand for speeding-up data communication, there has been proposed that a transmission packet, in which a guard time and a preamble portion of 16 bits for performing synchronization are arranged between a header PH and a payload PL as shown in FIG. 2, should be formed, an access code AC and the header PH should be sent by a frequency shift keying modulating signal, and the preamble portion PA and the payload PL should be sent by a phase-shift keying modulating signal.
In the case in which a former half of the transmission packet is sent by the frequency shift keying modulating signal and a latter half thereof is sent by the phase-shift keying modulating signal in this way, it is known that, since phase-shift keying modulation is adopted, carrier frequency shift (frequency offset) changes to phase demodulation distortion to significantly affect a bit error rate (BER).
As a compensation method for this frequency offset, there has been proposed a demodulation device for wireless data communication which is adapted to, when a lockup time for PLL is insufficient only during preamble reception, continuously perform differential detection in a data area of a frame to demodulate data and simultaneously perform an operation of the PLL to thereby compare data qualities of the differential detection and synchronous detection when the PLL lockup time has passed and select a suitable demodulation operation on a space transmission environment thereof (e.g., see Japanese Patent No. 3130773 (pages 1 to 4, FIG. 1)).
In addition, there has also been proposed an applied phase detection synchronization method such that an input signal is stored in a buffer memory once, and after applying trial mode processing, which estimates an angular frequency detuning degree and an initial phase difference and applicatively corrects a free-running angular frequency and an initial phase, to the stored input signal, performing normal mode processing which is conventional PLL processing to thereby realize an expansion of a synchronizing pull-in range of a PLL and a reduction in a noise band simultaneously (e.g., see Japanese Patent No. 2712706 (pages 1 to 10, FIG. 2)).
Similarly, there has been proposed a digital PLL circuit having a loop portion including phase comparing means, phase adjusting means, a loop filter, and a numerical control oscillator, which is adopted to find an average frequency error and phase error information from data for continuous n+1 symbols of phase data, which is continuously input to the phase comparing means, and start loop means when an average phase error is preset in the loop filter of the PLL circuit and phase information is preset in the numerical control oscillator to thereby calculate a time for loop pull-in (lock-in time) (e.g., see Japanese Patent No. 2877198 (pages 1 to 6, FIG. 2)).
However, when the above-mentioned transmission packet shown in FIG. 2 is received, since the preamble portion is as small as 16 bits, it is necessary to establish phase lock for phase-shift keying demodulation within a period of this preamble portion in switching the frequency shift keying modulating signal of the former half to the phase-shift keying modulating signal of the latter half.
In the conventional example described in Japanese Patent No. 3130773 (pages 1 to 4, FIG. 1), assuming a case in which frequency synchronization is not established by a preamble, the differential detection is performed during a period until the frequency synchronization is established, and the differential detection is switched to the synchronization detection after it is judged that a frequency is locked. However, since the differential detection is generally inferior to the synchronization detection in a bit error rate (BER) characteristic, in the case in which the differential detection is performed until the synchronization is established, it is likely that an error occurs in that period. Thus, in the short distance wireless data communication using the phase-shift keying modulation, since an error of 1 bit directly leads to a packet loss, there is an unsolved problem in that the packet loss increases.
In addition, in the conventional example described in Japanese Patent No. 2712706 (pages 1 to 10, FIG. 2), it is necessary to store an input signal in a buffer memory once because an initial value of a PLL is decided according to plural times of trial modes, and it is necessary to increase the number of times of trial modes in order to obtain a more accurate initial value. Thus, there is an unsolved problem in that required buffer memories increase in accordance with the increase in the number of times of trial modes, and a size of an overall structure increases.
Moreover, in the conventional example described in Japanese Patent No. 2877198 (pages 1 to 6, FIG. 2), delay means for finding a frequency initial value is required, and it is desirable to average a large number of bits in order to obtain a more accurate initial value. Thus, there is an unsolved problem in that a scale of a circuit increases.
Thus, the present invention has been devised directing attention to the unsolved problems of the conventional examples, and it is an object of the present invention to provide a wireless data communication demodulation device and a demodulation method which can accurately establish phase lock in a short preamble period.